1. Field of the Invention
The present invention relates to intermediate network nodes and, in particular, to a technique for efficiently performing address translation in an intermediate network node.
2. Background Information
A class of data networking equipment, referred to as Internet Protocol (IP)+ Asynchronous Transfer Mode (ATM) edge switches has emerged that are designed for service providers wishing to deploy IP (layer 3) services over narrowband and/or broadband services. These switches are designed to scale from DS0 to OC48c and support a multitude of services including frame relay, ATM, voice over ATM, Voice over IP (VoIP), wireless aggregation, Digital Subscriber Line (DSL) aggregation, ATM service backbones and Virtual Private Networks (VPN's). As the name implies, these routers reside at the edge of the network and provide a complete portfolio of differentiated services including IP (layer 3) services over ATM.
To support higher-level services, such as IP services over ATM, these edge switches typically incorporate functionality that allows the switch to quickly assemble ATM cells into ATM packets and process these packets at the layer 3 level. Often these switches incorporate special hardware that is targeted to processing incoming cells and performing packet reassembly in order to accelerate the process of packet assembly.
One aspect of ATM cell processing may involve translating a Virtual Path Identifier (VPI) and Virtual Channel Identifier (VCI) associated with the cell to an address that allows the cell to be reassembled into a packet. A content-addressable memory (CAM) is ideally suited to perform this translation because it can be programmed to map an address (e.g., a VPI/VCI combination) to an output value that in turn can be used to determine a translated address.
A CAM is a memory that is used to store binary data that is searchable on the basis of content. Typically, a CAM provides a “match mode” that permits all of data in the CAM to be searched to determine if a particular value is stored at one of the memory locations in the CAM. If the value is found, a “match” signal is typically asserted. In some CAM implementations, the address of the matching data is provided.
FIG. 1 illustrates a conventional address translation circuit comprising a CAM 120 connected to a random-access memory (RAM) 150. Both the CAM 120 and the RAM 150 are programmed by an external processor (not shown). The CAM 120 holds binary data that is representative of address values that are to be translated. The RAM holds the new (translated) address value.
Assume an address 110 is to be translated using the circuit illustrated in FIG. 1. Further assume the CAM has been programmed with an entry 130 that matches the address 110. The address 110 is supplied to the CAM 120. The CAM 120 searches its contents and locates the matching entry 130. The address of the matching entry 130 is used as an index (address) 140 to select a location in the RAM 150. The contents of the selected location contains the new address value 160. This new address value 160 is the value of the translated address.
As can be seen from this design, before address translation can be performed, both the CAM and the RAM need to be programmed, thus necessitating maintenance of two sets of data. Further, in a hardware implementation, logic needs to be provided to support both the CAM and RAM functions. In an environment where the number of gates available to implement a given design is limited, such as an ASIC, the amount of gates necessary to implement these functions may be impractical. It would be highly desirable to have a circuit that is capable of translating addresses with less programming and circuitry than the conventional address translation circuit.